Semiconductor memory devices can typically be classified on the basis of memory functionality, data access patterns and the nature of the data storage mechanism. For example, distinctions are typically made between read-only memory (ROM) devices and read-write memory (RWM) devices. The RWM devices typically have the advantage of offering both read and write functionality with comparable data access times. Typically, in RWM devices, data is stored either in flip-flops for "static" memory devices or as preset levels of charge on a capacitor in "dynamic" memory devices. As will be understood by those skilled in the art, static memory devices retain their data as long as a supply of power is maintained, however, dynamic memory devices require periodic data refreshing to compensate for potential charge leakage. Because RWM devices use active circuitry to store data, they belong to a class of memory devices known as "volatile" memory devices because data stored therein will be lost upon termination of the power supply. ROM devices, on the other hand, may encode data into circuit topology (e.g., by blowing fuses, removing diodes, etc.). Since this latter type of data storage may be hardwired, the data cannot be modified, but can only be read. ROM devices also typically belong to a class of memory devices known as "nonvolatile" memory devices because data stored therein will typically not be lost upon termination of the power supply. Other types of memory devices that have been more recently developed are typically referred to as nonvolatile read-write (NVRWM) memory devices. These types of memory devices include EPROM (erasable programmable read-only memory), E.sup.2 PROM (electrically erasable programmable read-only memory), and flash memories, for example.
An additional memory classification is typically based on the order in which data can be accessed. Here, most memory devices belong to the random-access class, which means that memory locations can be read from or written to in random order. Notwithstanding the fact that most memory devices provide random-access, typically only random-access RWM memories use the acronym RAM. Alternatively, memory devices may restrict the order of data access to achieve shorter data access times, reduce layout area and/or provide specialized functionality. Examples of such specialized memory devices include buffer memory devices such as first-in first-out (FIFO) memory devices, last-in first-out (LIFO or "stack") memory devices, shift registers and content-addressable memory (CAM) devices.
A final classification of semiconductor memories is based on the number of data input and data output ports associated with the memory cells therein. For example, although most memory devices have unit cells therein that provide only a single port which is shared to provide an input and output path for transfer of data, memory devices with higher bandwidth requirements often have cells therein with multiple input and output ports. However, the addition of ports to unit memory cells typically increases the complexity and layout area requirements for these higher bandwidth memory devices.
Single-port memory devices are typically made using static RAM cells if fast data access times are a requirement, and dynamic RAM cells if low cost is a primary requirement. Many FIFO memory devices use dual-port RAM based designs with self-incrementing internal read and write pointers to achieve fast fall-through capability. As will be understood by those skilled in the art, fall-through capability is typically measured as the time elapsing between the end of a write cycle into a previously empty FIFO and the time an operation to read that data may begin. Exemplary FIFO memory devices are more fully described and illustrated at section 2.2.7 of a textbook by A. K. Sharma entitled "Semiconductor Memories: Technology, Testing and Reliability", IEEE Press (1997).
In particular, dual-port SRAM-based FIFOs typically utilize separate read and write pointers to advantageously allow read and write operations to occur independently of each other and achieve fast fall-through capability since data written into a dual-port SRAM FIFO can be immediately accessed for reading. Since these read and write operations may occur independently, independent read and write clocks having different frequencies may be provided to enable the FIFO to act as a buffer between peripheral devices operating at different rates. Unfortunately, a major disadvantage of typical dual-port SRAM4-based FIFOs is the relatively large unit cell size for each dual-port SRAM cell therein. Thus, for a given semiconductor chip size, dual-port buffer memory devices typically provide less memory capacity relative to single-port buffer memory devices. For example, using a standard DRAM cell as a reference unit cell consuming one (1) unit of area, a single-port SRAM unit cell typically may consume four (4) units of area and a dual-port SRAM unit cell typically may consume sixteen (16) units of area. Moreover, the relatively large unit cells of a dual-port SRAM FIFO limit the degree to which the number of write operations can exceed the number of read operations, that is, limit the capacity of the FIFO.
To address these limitations of dual-port buffer memory devices, single-port buffer memory devices have been developed to, among other things, achieve higher data capacities for a given semiconductor chip size. For example, U.S. Pat. No. 5,546,347 to Ko et al. entitled "Interleaving Architecture And Method For A High Density FIFO", assigned to the present assignee, discloses a preferred memory device which has high capacity and uses relatively small single-port memory cells. However, the use of only single port memory cells typically precludes simultaneous read and write access to data in the same memory cell which means that single-port buffer memory devices typically have slower fall-through time than comparable dual-port memory devices. Moreover, single-port buffer memory devices may use complicated arbitration hardware to control sequencing and queuing of reading and writing operations.
U.S. Pat. No. 5,371,708 to Kobayashi also discloses a FIFO memory device containing an embedded single-port memory array, a read data register for holding read data from the memory array and a write data register for holding write data to the memory array. A bypass switch is also provided for transferring data from the write data register directly to the read data register so that the embedded memory array can be bypassed during testing of the FIFO to detect the presence of detects therein. However, like the above-described single-port buffer memory devices, simultaneous read and write access to data is not feasible.
Other attempts have also been made to develop high performance memory devices and techniques to test memory devices which may be embedded in an integrated circuit. For example, U.S. Pat. No. 4,404,519 to Westcott, entitled Testing Embedded Arrays in Large Scale Integrated Circuits, discloses an integrated circuit chip having an embedded array which is not directly accessible from the primary input/output pins. In particular, the disclosed integrated circuit is manufactured with additional test circuitry directly on the chip so that the performance of the array may be tested from the input/output pins by an external chip tester while the array remains embedded.
U.S. Pat. No. 4,481,627 to Beauchesne et al., entitled Embedded Memory Testing Method and Apparatus, discloses a method for testing memory arrays embedded within electronic assemblies having other combinational logic elements connected to the inputs thereof. The embedded memory can be isolated from the combinational logic elements and tested by use of a memory test subsystem. U.S. Pat. No. 4,969,148 to Nadeau-Dostie et al., entitled Serial Testing Technique for Embedded Memories, discloses a testing circuit which interfaces serially with the data path of an embedded memory circuit from at least one memory unit having separated data input and output lines and tandem addressing. Part of the testing circuit includes a series of two-input multiplexer units which are adapted to be embedded on the same chip as the memory circuit. The outputs of the multiplexer units connect to a respective one of the data input lines of the memory circuit. With the exception of the first bit position, a first input of each multiplexer unit is adapted to connect to the data output line of the adjacent bit position in the memory circuit. The second inputs of the multiplexer units are adapted to connect to the data bus of the chip. A finite state machine is also provided. This finite state machine is adapted to connect to the first input of the multiplexer unit at the first bit position and to the data output line at the least bit position. During testing, the finite state machine actuates the multiplexer units to connect the first bits, and for each address outputs a series of test bits, shifts those bits through the addressed word by a series of read and write operations, and examines those bits after their passage through the addressed word for defects in the memory circuit at that address. The finite state machine may or may not be embedded on the same chip as the memory circuit.
U.S. Pat. No. 5,331,643 to Smith, entitled Self-Testing Logic with Embedded Arrays, discloses shift register latch scan strings employed in a level sensitive scan design methodology for built-in circuit self-test. The scan strings are provided with bypassable portions which are made to serve as address registers for arrays which are embedded in blocks of logic for which the scan strings are meant to provide pseudo-random excitation test data. The bypassable portion of the scan strings is connected to an address stepper mechanism which insures complete coverage throughout the range of cell addresses within the array. This is accomplished through the utilization of a stepping counter or the utilization of a linear feedback shift register or similar mechanism so that every cell address in the array is provided with known pseudo-random data at the beginning of a test and which is also capable of providing array cell content information at the end of the test and/or at various times during test. In addition, U.S. Pat. No. 5,617,531 to Crouch et al., entitled Data Processor Having a Built-In Internal Self Test Controller for Testing a Plurality of Memories Internal to the Data Processor, discloses a data processor having a single test controller which includes a test pattern generator and a memory verification element. The test pattern generator generates and communicates a plurality of test patterns to the plurality of memories through a second storage device. A first storage device is used to store data read from the plurality of memories. The data from the first storage device is selectively accessed by the memory verification element via the bus. A bit or more than one bit is used to communicate whether the memories are operating in an error free manner.
Notwithstanding these attempts to provide techniques for testing memory devices containing embedded memory arrays, there still exists a need to develop improved techniques for operating and testing integrated circuits, such as memory devices having embedded memory arrays therein. There also exists a need to develop memory devices having increased functionality, increased data capacity and reduced unit cell size.